This invention relates to the fabrication of semiconductor devices by molecular beam techniques and more particularly to the fabrication of planar isolated devices, such as Schottky barrier mixer diodes and IMPATTs, by the simultaneous deposition of monocrystalline and polycrystalline Group III(a)-V(a) material.
Prior art attempts to grow planar isolated GaAs structures for multiple devices and integrated circuits have generally utilized selective chemical vapor deposition (CVD). As described by D. W. Shaw in two articles in the Journal of the Electrochemical Society, Vol. 113, page 904 (1966) and Vol. 115, page 777 (1968), the CVD process involves masking the surface of a semi-insulating GaAs substrate with SiO.sub.2 and removing the oxide in the areas where epitaxial growth is desired. A planar structure is achieved by etching holes several micrometers deep into the substrate in the unmasked areas. Shaw points out that since epitaxial growth by CVD requires a surface catalyzed reaction, deposition occurs only on the GaAs substrate and not on the SiO.sub.2 film. One disadvantage of the CVD process is that producing a planar geometry requires precise control of growth morphology and the rate of growth so that the epitaxial surface will be level with the SiO.sub.2 covered surface. In addition, the CVD process encounters the problem of facet growth as described by several workers in the art: Shaw, supra; S. Iida et al., Journal of Crystal Growth, Vol. 13-14, page 336 (1972); and Y. Isibashi et al. in two articles in Japan Journal of Applied Physics, Vol. 9, page 1007 (1970) and Vol. 10, page 525 (1971).
Viewed from another standpoint, the prior art problem can be defined in terms of device parameters. For example, in beam-leaded devices, such as Schottky barrier mixer diodes, which operate at highh frequencies in the tens off gigahertz range, parasitic capacitance inherent in the beam-leaded structure limits the diode efficiency. The parasitic capacitance arises because the beam anchor area and interconnects pass over the conducting substrate from which it is separated only by a thin insulating layer. This parasitic capacitance can be reduced by utilizing a mesa structure on a semi-insulating substrate. In the latter type of structure, the active device is formed on a mesa while the beam anchor area covers only the semi-insulating material. However, the fabrication of such mesa structures is difficult because it involves metallization and photoresist delineation of small details on a mesa which is typically 5 to 10 .mu.m high. Considerable process simplification could be realized if a planar device structure could be utilized.
In this regard, the previously described CVD process has been employed in an attempt to produce planar structures by the selective deposition of epitaxial material into the pits etched into a semi-insulating substrate. Difficulties have been encountered, however, in etching uniform pits for the deposition because etch rates are strongly affected by crystal orientation. Similarly, the crystal growth rate itself is orientation dependent and difficult to control. As a result, selective epitaxial areas are not coplanar with the substrate and tend to be nonuniform in thickness